1. Field of the Invention
This invention relates to the process monitor circuits in integrated circuit (IC) fabrication, and in particular, process monitor circuits for monitoring PMOS and NMOS transistors in a CMOS process.
2. Description of the Prior Art
A semiconductor die on a wafer often includes not only the product to be manufactured, but also a number of process monitor circuits which are fabricated on the die at the same time. The process monitor circuits are tested and their performance serves as a parametric test of the integrity of the manufacturing process. A process monitor circuit connected to the input and output pins of the integrated circuit on the die is particularly convenient because the pins are readily accessible by the test equipment. Having the process monitor circuit connected to the input and output pins of the integrated circuit on the die also allows the circuit to be tested at various steps of the manufacturing process, such as wafer sort, final test, at the end user, or wherever correlation of reliability data with process parameters is valuable.
In the past, one process monitor circuit used a relatively long path of logic gates for monitoring the circuit speed attained. Definitionally, a long path means any signal path in which the time delay of the path primarily results from the propagation delay of the internal logic circuits, and the time delay is only negligibly contributed to by external factors, such as output capacitive load, or the rise and fall times of the input signals. As internal logic paths are often not accessible directly from the input pins of the integrated circuits, a test structure including a long delay circuit is specially built for the purpose of testing, and included in the circuit to be fabricated. This long delay circuit often takes the form of a chain of serially connected inverters. Typically, such a chain may contain 50-100 inverters.
FIG. 1 shows a process monitor circuit in the prior art. As shown, the process monitor circuit includes a test structure 101, called a NAND tree, for measuring input buffer voltage thresholds of logic states (VIH and VIL). The NAND tree 101 is a chain of two-input NAND gates, with each NAND gate's two input terminals connected respectively to the output terminal of an input buffer, and the output terminal of the previous NAND gate in the chain. The first NAND gate of the chain has one input terminal connected to the power supply, and the other input terminal connected to the first input buffer of the NAND tree 101. Under this arrangement, the NAND tree 101 allows testing of each input buffer by applying a voltage at the input associated with each input buffer, and examining the output voltage at the output terminal of the last NAND gate in the NAND tree 101.
In the circuit shown in FIG. 1, the output terminal of the last NAND gate in the NAND tree 101 is connected to the delay logic path 102, similar to the delay circuit discussed above, consisting of 100 serially connected inverters. The output of the delay logic path 102 is provided through 2:1 multiplexor 103 at an output pad 104. In this test circuit, input buffer threshold voltages and the circuit speed attained are measured, respectively, by examining the voltage and the delays of signal transitions at output pad 104. Both tests may be conducted using the same input and output pins because the threshold voltage (VIH and VIL) measurements are not sensitive to circuit speed, which is measured by the propagation delay through delay logic path 102. This circuit speed is only negligibly affected by the propagation at the NAND tree 101, the input buffer 105 and the multiplexor 103. The input buffer 105, connected to the input pin "reset", toggles between the "test" mode and the "normal operation" mode of the integrated circuit. The inverted output signal of input buffer 105 selects for output one of the input signals of multiplexor 103. During the test mode, the output signal of delay path 102 is selected as the output of multiplexor 103, and during normal operation mode, the output signal on lead 106, which is provided by the functional circuitry of the integrated circuit on the die, is selected as the output of multiplexor 103. Hence, in this arrangement, each input pin of the die is dual-purpose, i.e. used as an input pin during testing, and also used as an input or output pin during normal operation. The output pin, such as output pin 104, is also dual-purpose, serving as an output pin during testing and as an output pin during normal operation.
In CMOS circuits, the performance of the integrated circuit depends on the performance of both PMOS and NMOS transistors. Since the PMOS and NMOS transistors are formed at different stages of the manufacturing process, variations in process factor at a given step may not affect the PMOS and NMOS transistors equally. As will be explained in the detailed description of the present invention, the performance of the delay logic path 102 does not provide information indicative of the different impacts of process factors on PMOS and NMOS transistors.
Hence, it is desirable to have a process monitor circuit indicative of the relative performance of the NMOS and PMOS circuits.